The invention generally relates to broadband communication systems for conveying digital data. More particularly, the invention relates to a programmable, general purpose Packet Processor, which can be used, for example, as a Media Access Control module for modems.
The recent development of the Internet, and the development of computer systems directed towards working in wide and global networks have significantly increased the use of modems. Modems for broad band communication are now required to deal with a very high rate of data transfer in a variety of environments.
In the previous decade, modems were mostly used for transferring digital data over a telephone line. In today""s communication systems, complex modems are also used for conveying data over other types of mediums, for example, over TV cables, or satellite links. Wireless and/or broad band modems are used, for example, in mobile communications, e.g., for communicating with cells or satellites, etc. Routers, which are widely used in networks, are also an example for such application.
The rapid development of modems for these and other purposes, and the fast and frequent increase in the data transfer rate have increased the necessity to frequently develop and define new standards and protocols for communications. The frequent introduction of new standards, and the increase in the transfer rate have generally required the replacement of older standards, by those compatible with the new standards, as the older modems could not comply with the newer standards, could not adapt to the change in the data transfer rate, or could not be reconfigured.
Generally, any modem comprises two main sections. The first section, the modulator-demodulator section, is a mixed signal section for interfacing between the modem and the medium of transfer, for example, a telephone line, TV cable, or the air, in the case of a wireless modem (hereinafter, when the term xe2x80x9cmodulator-demodulatorxe2x80x9d is used, it should be understood to refer to the above-indicated section of the whole apparatus called modem. When the term xe2x80x9cmodemxe2x80x9d is used, it should be understood to refer to the whole apparatus commonly called modem).
The second section of any modem is digital, generally referred to as the Media Access Control (MAC) module. The MAC module operates in the Media Access Control layer. The purpose of the MAC module is to manage and handle the transfer of digital data between the modulator-demodulator section of the modem and a host, in which the higher level layers are implemented, is generally located external to the modem casing, and vice versa.
The MAC module, is the heart of any modem. The MAC module receives a sequence of data stream from a host, creates packets of data that are then transmitted by the modulator, or receives such packets of data from the demodulator and creates a data sequence from them. Of course, these packets also contain additional information which the two communicating modems may need for assuring a reliable communication, i.e., for enabling the recovery of the data at the receiving end. More particularly, the Media Access Control handles error correction, regulates the data flow, handles the handshaking between the two modems, and optionally encrypts or decrypts the transferred data, when necessary, etc. Other functions of the MAC module, when used e.g., in a modem for TV cables are, to carry out the synchronization with the CMTS (Cable Modem Termination System), to manage upstream transmission allocation mechanism, to operate transmission of data on time slot boundaries, and to filter the received headers from the received data. Of course, the MAC module should comply with certain predefined standards, in order to enable the modem to properly communicate both with other modems, and with the host.
Of course, it is essential for the MAC module to handle its tasks in a fast and reliable manner, as the performance of the whole modem greatly depends on the performance of this module. In the existing modems, particularly those working at a very high rate, for example, modems for conveying digital data over TV cables, or those for communicating over fiber-optic links, this is not an easy task, as the amount and rate of the data that the MAC module has to handle are very high.
Efforts have been made to use a processing unit for carrying out many of the tasks of the MAC module, however, with limited success. High speed packet processing poses serious challenges to a single general purpose processor. This is the main reason why many existing modems use hard-wired logic for some of the lower level tasks of the MAC layer, while a high speed processor, if such exists, takes control only at the packet level or IP (Internet Protocol) level. More particularly, in the existing modems the data is processed by a plurality of gates for carrying out the MAC and packet handling tasks. This configuration is rigid, and cannot be changed or reconfigured when a necessity arises.
EP 789,468 discloses an adapter for wireless networks which provides for reconfigurable media access control and data packet formats. However, this adapter is suitable for lower end wireless LAN, and not for high data rate modems, such cable TV or satellite modems.
It is therefore an object of the present invention to provide a Packet Processor for communications applications, particularly for modems, which is capable of handling a high rate of data and performing the above-mentioned tasks in an efficient manner. It is a particular object of the invention to provide a Packet Processor for the broadband and wide band communication schemes, which is capable of implementing functions that must be handled in real time. In one particular case, the Packet Processor is used as a MAC module of a modem.
It is another object of the invention to provide a structure for said Packet Processor, for enabling it to easily adopt new communication standards, and change of data rate, when necessary.
It is still another object of the invention to enable this Packet Processor to communicate with different types of peripherals. In a particular case when the Packet Processor is used as a MAC module for modem, an object of the invention to enable it to communicate with different types of PHY (modulator-demodulator) chips.
It is still another object of the invention to provide said MAC module in a structure which can be easily integrated in a single Very Large Scale Integration (VLSI) chip.
It is still another object of the invention to provide a general-purpose media Packet Processor, which can be used in other communications applications, and for various purposes, due to its programming characteristics.
Other objects and purposes of the invention will become apparent as the description proceeds.
The Packet Processor of the invention achieves these and other objects by providing to it a new structure.
The present invention relates to a Packet Processor for a communication apparatus, for processing received and transmitted data streams made of packets, each packet mainly comprises a header and a payload section, which comprises,
(A) A receiving part comprising: (a) A receiving PHY interface by which a flow of data stream is conveyed from a Modulator-Demodulator section of a modem to the Packet Processor; (b) A receiving Tubular Bus receiving the said flow of data stream which is conveyed from the Modulator-Demodulator section of the modem to the Packet Processor, said receiving Tubular Bus conveying the data, while processed, in the direction from the said receiving PHY interface to a host interface; (c) At least one processing unit between sections of the said first Tubular Bus for sequentially receiving portions of a data stream from a section of the Tubular Bus processing the same, and outputting the processed data to a next section of the said first Tubular Bus; (d) One FIFO storage unit before and one FIFO storage unit after any of the said processing units on the receiving Tubular Bus, for providing a temporary storage for portions of the data stream; and (e) A first host interface for receiving data from the receiving Tubular Bus and conveying it to a host.
(B) A transmitting part comprising:
(a) A second host interface for receiving data from the host and conveying it to a second Tubular Bus; (b) A transmitting Tubular Bus for receiving the said flow of data stream which is conveyed from the host to the Packet Processor, said transmitting Tubular Bus conveying the data stream, while processed, in the direction from the said second host interface to a transmitting PHY interface; (c) At least one processing unit between sections of the said transmitting Tubular Bus, for sequentially receiving portions of the data stream from a section of the Tubular Bus, processing the same, and outputting the processed data to the next section of the said transmitting Tubular Bus; (d) One FIFO storage unit before and one FIFO storage unit after any of the said processing units on the second Tubular Bus, for providing a temporary storage for portions of the data stream; and (e) A transmitting PHY interface for receiving processed data from the transmitting Tubular Bus and conveying the same to a Modulator-Demodulator section.
(C) A Backbone Bus for conveying management data, instructions, and addresses between various components of the Packet Processor; and
(D) Timing and control means for administering the operation of the Packet Processor, and particularly the timing of using transmission slots for the transmit path.
Each one of the processing units in the Packet Processor functions independently, but simultaneously, with the other processing units of the packet processor.
Preferably, the first and second host interfaces are fabricated within a same interface.
Preferably, the module comprises two processing units in the receiving part and two processing units in the transmitting part. In this case, in the receiving part, the processing unit closer to the demodulator handles the tasks of mainly processing the header, deframing the data stream, and detecting and correcting errors (CRC) in the header of the received data stream. The processing unit closer to the host, mainly handles the tasks of logical analysis, including, determining the length and type of the packets (management, or data), possible concatenation of packets etc., decrypting (DES) the received data stream, and error detecting and correcting of the data portion of the data stream. In the transmitting part, the processing unit closer to the host mainly handles the tasks of timing, controlling allocation, and prioritizing the transmission sequences, and activities related to the creation of the header CRC of the transmitted data stream. The processing unit closer to the modem mainly handles the task creation of the main CRC, encryption (DES), and framing of the transmitted data.
Preferably, each processing unit comprises a processor and a co-processor and an internal memory, which comprises an Instruction Cache memory and a Scratch Pad RAM.
Preferably, the packet processor of the invention also has a connection to an external memory unit. In that case, the communication with the external memory unit is made by a processing unit of the Packet Processor, via the Backbone Bus, and an external bus arbiter.
Preferably, the Packet Processor also has a connection to one or more external devices. One of said external devices is a storage unit, containing the application code for operating the Packet Processor, said application code being downloaded into the internal memory of each processing unit of the Packet Processor, and into said external memory unit when initializing the Packet Processor.
More preferably, the Packet Processor further comprises an External Bus for communication of the module with an external memory unit. In that case, the communication is made by a processing unit of the packet processor, via the External Bus, and an external bus arbiter.
Preferably, the Packet Processor further comprises a debugging unit for assisting in the debugging of the packet processor.
Preferably, the Packet Processor further comprises a DMA (Direct Memory Access) control unit for enabling internal transfer of data blocks between internal components of the Packet Processor, and transfer of data blocks between internal components of the Packet Processor and components external to the Packet Processor by means of the host interface.
The Packet Processor of the invention can be fabricated in a VLSI form.
Preferably, the Packet Processor of the invention further comprises a Serial Interface, preferably programmable, for carrying out communication of the Packet Processor with external serial components. Furthermore, it preferably comprises an Interrupt Central Unit (ICU) for handling interruptions to components in the Packet Processor.
The Packet Processor of the invention is particularly useful in modems, for example, a modem for TV cables. A particular use of the packet processor is as a Media Access Control for a modem for TV cables. However, it can also be used in many other communication applications, such as in wireless LANs, IP (Internet Protocol) telephones, or in routers of computer networks.
Preferably, each processing unit can send one or more macro-instruction, embedded with the data flowing in the tubular bus, said macro instruction flowing with the data stream over the tubular bus to a destination component downstream the tubular bus, and is used for controlling said component. A macro instruction may be provided, for example, to a FIFO, for flushing it, and for instructing it to ignore a portion of an incoming data, for example when an error is detected in the data, which cannot be corrected.
Preferably, the second FIFO downstream the receiving bus further has an associated address filter, said address filter which is used for comparing a destination address that is detected in the data stream with a list of addresses stored in said address filter, and according to the result of the comparison, a determination is made whether an operation should be taken or not on at least a portion of the data stream. Many different types of operations may be made based on said comparison, for example, an ignoring of a portion of the data stream.
Preferably, each of the said processing units is a RISC processor. More preferably, each processing unit is of the ARC type processor.